Integrated circuit design is a vastly complex effort. Frequently, millions and even hundreds of millions of transistors can exist on a single semiconductor chip. The ability to design chips with this many transistors can be quite challenging and optimizing the circuitry as needed can be a daunting task even with the help of electronic design automation (EDA) software tools.
Hierarchy within a chip can be used to enable design of a portion of a chip and then to design interconnections between the various portions. Leaf cells can be the lowest level of logic, such as AND, OR, NAND, NOR, XOR, and XNOR gates. These types of gates are combinational logic where the output is a function of the inputs at any given time. Leaf cells can also include flip flops which are memory elements. These flip flops and other memory components make up sequential logic. The output of sequential logic is a function of the current inputs and what has occurred to that sequential logic over a period of time.
Logical hierarchy can represent different logical functions of a chip which can in turn be combined at higher levels of hierarchy. Physical hierarchy can represent different geographical regions of a chip. A single logical function can be spread across multiple geographical locations on a semiconductor chip.